Conventional or bulk semiconductor devices are formed in semiconductive material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid undesired short circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate increase power consumption, require higher threshold voltages, and slows the speed at which a device using such transistors can operate (e.g. degrades frequency response). These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance problem and improve frequency response, silicon on insulator technology (SOI) has been gaining popularity. A SOI wafer is formed from a bulk silicon wafer by using conventional oxygen implantation or bonded wafer techniques to create a buried oxide layer at a predetermined depth below the surface. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a guassian distribution pattern centered at the predetermined depth to form the buried oxide layer.
An SOI field effect transistor comprises two separated impurity regions consisting of the source and drain regions of the transistor of a first semiconductor conductivity and a channel region between them of the opposite semiconductor conductivity covered by a thin gate insulator and a conductive gate. In operation, a current can flow between the source and drain through the channel region when the channel region is depleted by applying a voltage in excess of the threshold voltage to the conductive gate. A problem with SOI FET's is that the channel region between the source and drain is electrically floating because the source and drain regions normally extend entirely through the thin silicon layer to the buried oxide insulating layer. This effect is known as the floating body effect and can cause instability and unpredictable operation because the floating body potential affects the FET threshold voltage and affects the current flow through the FET for a particular gate voltage.
For example, referring to FIG. 1, it can be seen that a conventional N-channel (P-type) SOI FET 10 includes a lightly doped P-type conductivity body region 12 and an N-type source region 14 and drain region 16. A source/body junction 32 and a drain/body junction 34 are on opposing sides of the body region 12. The source region 14 and the drain region 16 extend entirely from the surface to the buried oxide layer 24 such that the body region 12 is entirely isolated from the silicon substrate 26. A gate oxide 18 and polysilicon gate 20 define the FET channel region channel 22 across the body region 12 between the source region 14 and the drain region 16.
In operation of FET 10, when gate electrode 28 is pulled high, free electron carriers 30 accumulate in the channel region 22 below the gate oxide 18 which enables free electron current flow across the channel between the source 14 and the drain 16. When the gate electrode is low, the channel region 22 depletes and a reverse biased junction at the source/body junction 32 and at the drain/body junction 34 exists. The reverse biased junctions prevent current flow between the source region 14 and the drain region 16.
Because of reverse bias current leakage across the source/body junction 32 and/or across the drain/body junction 34, the body region 12 may charge to a positive potential, up to Vdd, in some cases, by the accumulation of holes in the channel region. This charge accumulation is unpredictable and it makes operation of the FET unpredictable because charge accumulation effects: (1) current leakage between the source region 12 and drain region 16 across the junctions when the FET 10 is turned "OFF"; (2) transient bipolar current flows from the source region 14 to the drain region 16 when the FET 10 is turned "OFF"; (3) the current flow across the channel region 22 when a Vdd potential is applied to the gate electrode to turn the FET "ON"; and (4) the rate at which such current flow "ramps up" when the FET 10 is turned on.
Such unpredictability effects are particularly problematic for FETs used in static random access memory SRAM cells and other devices where it is critical that the FET threshold voltage remain controlled to control operating speed, access time, and or OFF state drain current.
Accordingly, there is a strong need in the art for a semiconductor field effect transistor structure, and a method for forming such structure, that includes the low junction capacitance characteristics of the SOI FET but does not suffer the disadvantages of being unpredictable due to the floating body effect.